Recent technological advances have led to complementary metal-oxide-semiconductor (CMOS) sensor imagers being leveraged by cameras, video systems, and the like. CMOS sensor imagers can include an integrated circuit with an array of pixel sensors, each of which can comprise a photodetector. Moreover, a CMOS sensor imager can be incorporated into a System-on-Chip (SoC). As such, the SoC can integrate various components (e.g., analog, digital, . . . ) associated with imaging into a common integrated circuit. For instance, the SoC can include a microprocessor, microcontroller, or digital signal processor (DSP) core, memory, analog interfaces (e.g. analog to digital converters, digital to analog converters), and so forth.
Visible imaging systems implemented using CMOS imaging sensors can reduce costs, power consumption, and noise while improving resolution. For instance, cameras can use CMOS imaging System-on-Chip (iSoC) sensors that efficiently marry low-noise image detection and signal processing with multiple supporting blocks that can provide timing control, clock drivers, reference voltages, analog to digital conversion, digital to analog conversion and key signal processing elements. High-performance video cameras can thereby be assembled using a single CMOS integrated circuit supported by few components including a lens and a battery, for instance. Accordingly, by leveraging iSoC sensors, camera size can be decreased and battery life can be increased. Also, dual-use cameras have hence emerged that alternately produce high-resolution still images or high definition (HD) video.
The advantages offered by System-on-Chip integration in CMOS visible imagers for emerging camera products have spurred effort to further improve active-pixel sensor (APS) devices. Active-pixel sensors with on-chip analog and/or digital signal processing provide temporal noise superior to scientific-grade video systems using charge-coupled device (CCD) sensors. Sophisticated iSoCs, on the other hand, are vulnerable to noise pickup inside the sensor that can increase random and fixed pattern noise. Moreover, contrasting clocking frequencies (e.g., μs to tens of ns), capacitive loads (e.g. from a few pF to a few nF), bandwidths (e.g., few MHz to GHz), and slew rates pose a significant challenge for designing a comprehensive low noise reference generator. Another consideration for maximizing image quality is the need to mitigate spurious noise events that potentially can cause cross-talk between reference voltage components. Accordingly, conventional voltage generation techniques oftentimes fail to deliver low noise reference voltages on large integrated circuits such as, for example, when the integrated circuits are complex iSoCs.